This invention relates to a method of controlling the flows of current in driving brushless motors with constant turn-off period Toff.
More particularly, the invention relates to a current control method for drive systems of multi-phase brushless motors, particularly at phase switching, wherein the motor coils led to a common node are driven each by applying a respective drive voltage to the free end of each coil via corresponding power stages.
The invention broadly concerns the driving of three- or multi-phase motors by the constant Toff current control methodology.
A most frequently used methodology for driving three-phase motors or, more generally, multi-phase motors is known as the constant turn-off time Toff methodology.
FIG. 1 herein shows schematically the construction of a three-phase electric motor and its electronic driver circuit. Of course, this motor includes three coils 1, 2 and 3 which are Y-connected at a common node D. Half-bridge stages 4, 5 and 6 are connected to the opposite ends A, B and C, respectively, of each coil.
Each stage 4, 5 or 6 comprises a pair of DMOS power transistors Dm1, Dm2 which are driven from respective outputs of a corresponding driver circuit 13. Each transistor has an intrinsic diode associated therewith.
The half-bridge stages 4, 5 and 6 are usually connected together in parallel between a supply voltage reference Vs and a ground-connected sense resistor 7.
A comparator 8 has one input connected to the interconnection node between the resistor 7 and said stages 4, 5 and 6, and has the other input maintained at a reference potential Vref.
The output of the comparator 8 is connected to an input IN of an astable circuit 9. This astable circuit 9 is asked to generate a signal Toff corresponding to a predetermined turn-off time period. For the purpose, the astable circuit is connected to a parallel RC circuit comprising a resistor 10 and a capacitor 11.
The comparator 8 controls the current I=Vrf/Rsense which is flowing through the sense resistor 7 and, hence, through the motor coils. Decoding logic 12 is arranged to process information received on corresponding logic inputs and the signal received by the astable circuit 9. The logic 12 delivers a corresponding signal to each driver circuit 13 of the coils 1, 2 and 3 to control the motor rotation.
The aspects of the invention may be made clearer by an explanation of how a motor rotates under constant Toff control.
A half-bridge stage is regarded to be in the xe2x80x9coffxe2x80x9d state when the corresponding transistor Dm2 is xe2x80x9conxe2x80x9d while the other transistor Dm1 is xe2x80x9coffxe2x80x9d. This condition is illustrated schematically by FIG. 2, where current paths 14, 15 and 16 are shown to represent flows to be explained.
On the other hand, a half-bridge is regarded to be in the xe2x80x9conxe2x80x9d state when the transistor Dm2 is xe2x80x9coffxe2x80x9d while the transistor Dm1 is xe2x80x9conxe2x80x9d.
When both transistors Dm1 and Dm2 are in the xe2x80x9coffxe2x80x9d state, the half-bridge is in a tristate mode.
The driver circuit 13 is able to control a current I1 in the branches 1-2 when this current I1 is flowing from the terminal A to the terminal B of the coils 1 and 2, while no current is flowing through the coil 3 (FIG. 3.1 ). On the contrary, the current I1 will flow through the branches 2-1 when the controlled current I1 is flowing from the terminal B to A with no current being present in the coil 3 (FIG. 3.4).
Assume the half-bridge 6 to be at a high impedance, half-bridge 5 to be xe2x80x9coffxe2x80x9d, and half-bridge 4 xe2x80x9conxe2x80x9d. In this situation, a current I flowing through the coils 1-2 would have a time constant given as:   τ  =            L1      +      L2              Rdm1      +      Rdmn2      +      Rl1      +      Rl2      
where: L1, L2, R11 and R12 are inductance and parasitic resistance values, respectively for the coils 1 and 2, while Rdm1 and Rdm2 are the resistances of the xe2x80x9conxe2x80x9d DMOS transistors in the half-bridges 4 and 5.
This current I causes the voltage across the resistor 7 to increase. Upon this voltage reaching the same value as the reference voltage Vref, the comparator 8 and astable circuit 9 will generate the constant time signal Toff.
Two different actions can be made during this phase. In particular, the current control is said to be in the fast decay mode if, during the period Toff, all the half-bridges are in the tristate mode and the inductive load current is looped back through the intrinsic diodes associated with the transistor Dm1 of the half-bridge 5 and the transistor Dm2 of the half-bridge 4 (path 14 in FIG. 2).
The current control is said to be in the slow decay mode if, during the period Toff, both half-bridges 4 and 5 are xe2x80x9conxe2x80x9d while the half-bridge 6 is in the tristate mode. The decay time is here longer than in the former case, since the reverse voltage being applied to the coils 1 and 2 is lower.
After the time period Toff, the cycle sets out again from the start condition.
The peak current I1 flowing through the coils 1-2 is thus controlled. The same will occur as the currents in the branches 1-3 and 2-3 and the respective reverse directions 2-1, 3-1 and 3-2 are controlled.
The control logic 12 controls rotation by controlling the current in the order shown quite clearly in FIGS. 3.1, . . . ,3.6. For example, in the forward direction, the phase switching order is: 1-2; 1-3; 2-3; 2-1; 3-1; 3-2.
These figures show schematically the current flows that enable the rotation of a three-phase motor to be controlled in the forward and reverse directions. The rotational speed of the motor is equal to the rate of phase switching dictated by the control logic 12.
Let the case be considered of the current control being shifted from the branch 1-2 to the branch 1-3.
A single plot in FIG. 4A illustrates the patterns of different voltage and current signals present in the motor.
The moment that a change in phase is decided, the half-bridge 5 driving the coil 2 is forced into the tristate mode, allowing the regulated current I1 to loop back through the respective intrinsic diode of the transistor Dm1. Simultaneously therewith, the half-bridge 4 is held xe2x80x9conxe2x80x9d, and the half-bridge 6 enters the xe2x80x9coffxe2x80x9d state to increase the current in the coil 3. In this condition, considering the state of each half-bridge and the direction of the current at the time when the phase is changed, the following conditions apply to the voltages at the nodes A, B and C:
1) node A voltage:
VA=Vccxe2x88x92I*Ron, where RON is the turn-on resistance of the transistor Dm1 of the half-bridge 4, and Vcc is the supply voltage;
2) node B voltage:
VB=Vcc+Vbe, where Vbe is the voltage at the intrinsic diode of the transistor Dm1 of the half-bridge 5;
3) node C voltage:
4) VC=0 because the current is nil at the start of the phase change in the coil 3.
Assuming, as the least favorable of cases, that the three coils can be considered as purely inductive loads, the Dmos resistance is negligible, and the supply voltage Vcc is so high that the drop across the intrinsic diode of the Dmos transistors can be ignored, then the voltages at the nodes A, B, C and D are given as:
VA=Vcc; VB=Vcc; VC=0; VD=⅔*Vcc.
FIG. 4 shows clearly that these values are attained at the end of the phase change.
Since the voltage at the coil 3 is twice higher than that on the coils 1 and 2, the rate of current increase in the inductor 3 will be twice as high as the rate of increase (or decrease) of the current in the coil 1 (or 2).
Accordingly, the state of the half-bridges 4, 5 will remain in this condition until the current in the half-bridge 6, and hence in the sense resistor 7, reaches the value of the regulated current I=Vref/Rsense.
As a result, upon the current 13 reaching the required value I in the branch 3, the current 12 in the branch 2 will reach a value 0.5*I and the current I1 in the branch 1 a value 1.5*I.
As shown in FIG. 4A, the current I1 in the branch 1 attains a higher value than the regulated current I. The phase switch forces the current I1 to increase in the branch 1, and therefore, a power loss is obtained by dissipation through the Dmos transistor Dm1 of the half-bridge 4 and the coil 1.
Furthermore, if the control current I is the largest acceptable current for the motor, half-bridge stages must be selected whose Dmos transistors can sustain currents which are 1.5 times larger than the maximum control current I provided, entailing increased consumption and manufacturing costs.
In addition, as the branch 1-2 begins to regulate the current I, the branch 3 decay takes place after a number of cycles of period Toff, and this in either the fast or the slow decay mode.
Also, where protection circuits for detecting the largest current being flowed through the Dmos transistors are provided, the protection circuits must be calibrated for a protection current which is at least 1.5 times the maximum control current I provided in the motor, which intensifies cost.
An embodiment of this invention provides a methodology for controlling the current flows during the drive phases of brushless-type electric motors, particularly upon phase switching, which is effective to overcome the aforementioned drawbacks of the prior art, ensure improved control of the current in the motor coils, and reduce power dissipation during such phase switching. The embodiment forces the current flow switched from one phase to the next phase according to the direction of rotation of the motor, by forcing the coil being turned off in the next phase into a state of high impedance during the phase switch.